Flare
Load Testing for Evolved Packet Core (ePC/VePC)
Load and functional testing of ePC elements such as: MME, SGSN, GGSN, SGW, PGW. End-to-end testing and interworking. Emulation of ePC neighboring systems (e.g. eNodeB, CGF, HLR, HSS, STP, DRA, PCRF, OCS, AAA, RNC, …). End-to-end with or without L4-7 data.
Absolute functional flexibility + 1,000,000 MSU/s performance
Need 2 mils? No problem, just tell is.
|
Linkbit Flare is designed for load testing of Evolved Packet Core (ePC) networks, and the upcoming VePC deployments. It is based on the technology initially develped for Linkbit functional testers, and as a result is extremely flexible. While retaining all the functional testing flexibility of PacketCraft, Flare adds to the mix a massive load generation capability. Flare's highly scalable software architecture allows for delivery of practically unlimited TPS load numbers for any of the EPC stacks. Flare is available as a stand-alone COTS blade-server or virtualized in the cloud. |
|
|
|
Why Flare is different?
For far too long conflicting requirements of functional vs load testing forced MNOs to purchase and learn different, incompatible tools. This is no longer necessary, as Linkbit Flare delivers practically unlimited load performance without sacrificing the extreme flexibility provided by Linkbit functional testing technology.
By making it possible to execute Linkbit proprietary packet processing engine on multiple physical or virtual Linux nodes in parallel, Linkbit has created the test platform ideally suitable for performing any mixture of load and functional testing in MNOs core networks.
Flare is programmed with XDL
Linkbit XDL (eXecutable Diagram Language) is a network centric visual Domain Specific Language (DSL) for programming of high-performance packet flows. XDL source code is a directed graph. The edges of the graph indicates control flow, while vertices send/receive network traffic and perform data operations. The language supports automatic parallelization and is highly scalable. Load generation capabilities are only limited by number of available CPU nodes (cores) and a clock frequency of individual nodes.